This invention relates to a device for controlling memories according to an interleave system. Interleave systems are used with memories so that they appear to operate faster than their normal speed. In interleave systems, memory is divided into several memory blocks or banks which can be accessed simultaneously and independently.
FIG. 1 shows an interleave system with N independent memory blocks #1 through #N coupled to bus 10. This interleave system is most effective when:
(i) microprocessor 13 performs memory access continuously by accessing different memory blocks; and
(ii) a memory block is not accessed during a memory cycle.
For example, for four memory blocks each having a cycle time of 3t (corresponding to 3 steps), the ideal operating condition is as shown in FIG. 2. FIG. 2a shows a system execution clock pulse. Memory block #1 is accessed using the clock pulse provided at time t1 which starts the memory cycle as shown in FIG. 2b. The cycle time is equal to 3t, so the particular memory cycle for this access ends at time t4. At the end of that cycle, data is read from the memory to bus 12 as shown by the pulse labeled #1 in FIG. 2(z).
Memory block #2 is accessed using the clock pulse at time t2. Similarly, memory blocks #3 . . . #N are accessed cyclically at successive one clock pulse time intervals. The memory cycles for memories #2-#4 are shown by FIGS. 2(c)-(e), and the next cycle of memory #1 is shown in FIG. 2(f). The data outputted for these memories appears at the time indicated by the correspondingly numbered pulses in FIG. 2(z).
If, in the memory device employing this interleave system, an attempt is made to access a memory block which is currently in its memory cycle, memory accessing must be stopped. lf the memory block is a DRAM (Dynamic Random Access Memory), memory accessing must also be stopped during refresh. In addition, the memory control for such a system must also solve the problems which occur due to the suspension of memory accessing.
For example, if that interleave system employs the program shown in FIG. 3, and both the first and second memory accesses are given to the same memory block, serious problems arise. For example, assume the first read access request #1--1 is given to memory block #1 at system execution clock time t1 as shown in FIG. 4(a). At the next execution clock time t2, assume that memory access #1-2 is also given to memory block #1 (Step 2 of FIG. 3 and FIG. 4(c)). Since memory accessing had already started in response to the first request, memory block #1 is occupied during the period indicated in FIG. 4(b), and the system execution clock pulse is masked for periods t2 and t3. The second read access request #1-2 is placed in a waiting state since memory execution is effectively stopped. If, in addition, the third read access request #1-3 is given to memory block #1 at system execution clock time t5 (Step (3) of FIG. 3), then the third read access request is also placed in a waiting state.
In this memory system, the actual reading of the data is performed at the end of the first memory cycle as shown in FIG. 4(e). Since the system execution clock pulse is masked, processor 13 does not fetch data until time t8, when the cycle time ends (FIG. 4(f), Step (4) in FIG. 3). Reading and fetching the other data are performed in the same manner (Steps (5) and (6) in FIG. 3).
As is apparent from the above description, when the conventional memory system performs memory control according to this interleave system, it must have devices such as registers, or memory units, for temporarily storing the data read out from the memory blocks. The greater the number of memory blocks, the greater the number of the devices which are required. This increase in the number and complexity of devices is both expensive and complex.
An object of this invention is a memory control device which temporarily stores, in a single position, data read out of a memory block in an interleave system.